1. Field of the Invention
The present invention relates to a digital filter and, more particularly, to a digital filter for use in a video emphasis circuit of, for example, a magnetic recording/reproducing apparatus.
2. Description of the Related Art
For instance, according to a magnetic recording/reproducing apparatus which executes data recording/reproduction by using video signals of a NTSC system, a luminance signal acquired by Y/C separation is used for FM modulation at the time of data recording. At the time of data reproduction, however, a luminance signal separated from a reproduced video signal is subjected to FM demodulation.
It is known that, in executing FM modulation/demodulation, the high-frequency component of a modulation signal is subjected to emphasis in advance prior to FM modulation at the time of recording, and the high-frequency component of an FM demodulation signal is reduced at the time of reproduction to thereby improve the SN ratio of a luminance signal. The former is called pre-emphasis, and the latter de-emphasis. To perform these processes, therefore, a conventional magnetic recording/reproducing apparatus is provided with a video emphasis circuit generally constituted by an analog filter, i.e., a pre-emphasis circuit and de-emphasis circuit.
Recently, to provide a high-quality image, a digital signal processing technique is applied to a magnetic recording/reproducing apparatus and the pre-emphasis and de-emphasis circuits are realized by a digital filter, particularly, an infinite pulse response (IIR) type digital filter.
The transfer functions of the pre-emphasis and de-emphasis circuits are given by a quotient of a numerator polynomial and a denominator polynomial (hereinafter simply called "numerator" and "denominator"), i.e., by a rational function; the denominator and numerator are typically processed by a single common circuit.
To execute an emphasis process in the order of the denominator and numerator in a common or shared video emphasis circuit, therefore, it is necessary to use a denominator processor with a great dynamic range because the DC component of the signal processed in de-emphasis mode has a large gain. To execute the emphasis process in the order of the numerator and denominator, however, the dynamic range of a numerator processor becomes large because the high-frequency component of the signal processed in pre-emphasis mode has a large gain. This requires a denominator processor with a large dynamic range. Accordingly, irrespective of the order the process is carried out, the denominator processor should have a large dynamic range. When the acquired output signal is binary-transformed, therefore, the number of bits increases and the data processing time becomes long accordingly. This makes it difficult to use, particularly, an IIR type filter which needs a short processing time.